English
Language : 

80333 Datasheet, PDF (1/75 Pages) Intel Corporation – I/O Processor
Intel® 80333 I/O Processor
Datasheet
Product Features
■ Integrated Intel XScale® core
— 500, 667 and 800 MHz
— ARM* V5TE Compliant
— 32 KByte, 32-way Set Associative
Instruction Cache with cache locking
— 32 KByte, 32-way Set Associative Data
Cache with cache locking. Supports
write through or write back
— 2 KByte, 2-way Set Associative Mini-
Data Cache
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 4-Entry Fill and Pend Buffer
— Performance Monitor Unit
■ Internal Bus 333 MHz/64-bit
■ PCI Express*-to-PCI Bridges
— x8 PCI Express* Upstream Link
— PCI Express* Specification 1.0a
compliant
— PCI-X Bus A (IOP bus - ATU interface)
— PCI-X Bus B (Slot Expansion bus)
supports standard PCI Hot-Plug
Controller
— Four output clocks per PCI-X bus
■ Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
— Connects Internal Bus to PCI/X Bus A
— Messaging Unit and Expansion ROM
■ Two Programmable 32-bit Timers and
Watchdog Timer
■ Eight General Purpose I/O Pins
■ Two I2C Bus Interface Units
■ Dual-Ported Memory Controller
— PC2700 Double Data Rate (DDR333)
SDRAM
— DDRII 400 SDRAM
— Up to 2 GB of 64-bit DDR333
— Up to 1 GB of 64-bit DDRII400
— Optional Single-bit Error Correction,
Multi-bit Detection Support (ECC)
— Supports Unbuffered or Registered
DIMMs and Discrete SDRAM
— 32-bit memory support
■ DMA Controller
— Two Independent Channels Connected
to Internal Bus
— Two 1KB Queues in Ch0 and Ch1
— CRC-32C Calculation
■ Application Accelerator Unit
— RAID6 support
— Performs optional XOR on Read Data
— Compute Parity Across Local Memory
Blocks
— 1 KB/512 byte Store Queue
■ Two UART (16550) Units
— 64-byte Receive and Transmit FIFOs
— 4-pin, Master/Slave Capable
■ Peripheral Bus Interface
— 8-/16-bit Data Bus with Two Chip Selects
■ Interrupt Controller Unit
— Four Priority Levels
— Vector Generation
— Sixteen External Interrupt Pins with
High Priority Interrupt (HPI#)
■ 829-Ball, Flip Chip Ball Grid Array (FCBGA)
— 37.5 mm2 and 1.27 mm ball pitch
Order Number: 305433, Revision: 003US
July 2005