80333 Datasheet, PDF (65/75 Pages) Intel Corporation – I/O Processor

80333
4.4.4
Table 32.
4.4.5
I²C/SMBus Interface Signal Timings
I²C/SMBus Signal Timings
Symbol
Parameter
Std. Mode
Min. Max
Fast Mode
Min.
Max
F_SCL
T_BUF
SCL Clock Frequency
Bus Free Time Between STOP and
START Condition
0
100
0
400
4.7
1.3
T_HDSTA Hold Time (repeated) START Condition
4
0.6
T_LOW SCL Clock Low Time
4.7
1.3
T_HIGH SCL Clock High Time
4
0.6
T_SUSTA
Setup Time for a Repeated START
Condition
4.7
0.6
T_HDDAT Data Hold Time
0
3.45
0
0.9
T_SUDAT Data Setup Time
250
100
T_SR SCL and SDA Rise Time
1000 20 + 0.1C_b 300
T_SF SCL and SDA Fall Time
300 20 + 0.1C_b 300
T_SUSTO Setup Time for STOP Condition
4
0.6
Notes:
1.
See Figure 9, “I2C/SMBus Interface Signal Timings” on page 70.
2.
Not tested.
3.
After this period, the first clock pulse is generated.
4.
5.
CSt_{bd.=MthoedetoIt2}aCl csaipgancailtatinmciengosf
one bus
apply for
line, in pF.
SMBus timing.
Units Notes
KHz
µs
(1)
µs (1, 3)
µs (1, 2)
µs (1, 2)
µs
(1)
µs
(1)
ns
(1)
ns (1, 4)
ns (1, 4)
µs
(1)
UART Interface Signal Timings
Table 33.
UART Signal Timings
Symbol
Parameter
Std. Mode
Min. Max
Units Notes
T_XD1 Ux_TXD output delay from M_CK rising edge
60
ns
1
T_RXS1 Ux_RXD data setup time (to M_CK rising edge).
50
ns
2
T_RXH1 Ux_RXD data hold time (to M_CK rising edge).
50
ns
2
T_CTS1 Ux_CTS setup time (to M_CK rising edge).
60
ns
T_CTH1 Ux_CTS hold time (to M_CK rising edge).
60
ns
T_RTS1 Ux_RTS setup time (to M_CK rising edge).
60
ns
T_RTH1 Ux_RTS hold time (to M_CK rising edge).
60
ns
Notes:
1.
See Figure 10, “UART Transmitter Receiver Timing” on page 70.
2.
All timings referenced to M_CK for functional testing, is for cases where M_CK × N = IBCLK.
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
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