80333 Datasheet, PDF (31/75 Pages) Intel Corporation – I/O Processor

80333
Table 15.
Power and Ground Pins
Name
V_CCPLL[1-5]
V_CC33
V_CC25/18
V_CC15
V_CC13
PE_VCCBG
DDR_VREF
V_SS
V_SSA[1-5]
PE_VSSBG
Count
5
49
29
56
7
1
1
218
5
1
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
Description
PLL 1-5 Power is a separate V_CC15 supply ball for the phase lock
loop clock generator. It is to be connected to the board V_CC15 plane.
Each V_CCPLL requires a low-pass filter circuit to reduce noise-
induced clock jitter and its effects on timing relationships. See the
Intel^® 80333 I/O Processor Design Guide for more information.
3.3 V Power balls to be connected to a 3.3 V power board plane.
2.5 V/1.8 V Power balls to be connected to a 2.5 V or 1.8 V power
board plane, dependent on DDR or DDRII mode.
1.5 V Power balls to be connected to a 1.5 V power board plane.
VCC15 = core
VCC15E = PCI Express*
1.3 V Power balls to be connected to a 1.35 V power board plane.
PCI Express* Band Gap Analog Ref Power: 2.5 V power for
analog reference circuit, separated from all other VCC signals.
Requires a low-pass filter.
SDRAM Voltage Reference is used to supply the reference voltage
to the differential inputs of the memory controller pins.
Ground balls to be connected to a ground board plane.
Analog Ground balls need to be connected to the appropriate
V_CCPLL filter, and not to board ground.
PCI Express* Band Gap Analog Ground: Ground for analog
reference circuit, separated from all other VSS signals.
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
31