80333 Datasheet, PDF (34/75 Pages) Intel Corporation – I/O Processor

80333
Table 16.
Pin Mode Behavior (Sheet 3 of 4)
Pin
Reset
Norm
ECC
Off
32-Bit
DDR
32-Bit
B_PCI
32-Bit
A_PCI
B_PERR#
Z
VB
-
-
-
-
B_M66EN
VB
VB
-
-
-
-
B_PME#
VI
VI
B_PCIXCAP
VI
VI
-
-
-
-
B_CLKO[4:0]
VO
VO
-
-
-
-
B_CLKOUT
VO
VO
-
-
-
-
A_AD[63:32]
Z
VB
-
-
-
H
A_AD[31:0]
0
VB
-
-
-
-
A_PAR
0
VB
-
-
-
-
A_PAR64
Z
VB
-
-
-
H
A_C/BE[3:0]#
0
VB
-
-
-
-
A_C/BE[7:4]#
Z
VB
-
-
-
H
A_REQ64#
VO
VB
-
-
-
-
A_ACK64#
Z
VB
-
-
-
-
A_FRAME#
Z
VB
-
-
-
-
A_IRDY#
Z
VB
-
-
-
-
A_TRDY#
VO
VB
-
-
-
-
A_STOP#
VO
VB
-
-
-
-
A_DEVSEL#
VO
VB
-
-
-
-
A_SERR#
Z
VB
-
-
-
-
A_RST#
VO
VO
-
-
-
-
A_PERR#
Z
VB
-
-
-
-
A_LOCK#
Z
VB
-
-
-
-
A_CLKO[3:0]
VO
VO
-
-
-
-
A_CLKOUT
VO
VO
-
-
-
-
A_CLKIN
VI
VI
-
-
-
-
A_M66EN
VB
VB
-
-
-
-
A_PME#
VI
VI
A_REQ[3:0]#
VI
VI
-
-
-
-
A_GNT[3:0]#
H
VO
-
-
-
-
A_PCIXCAP
VI
VI
-
-
-
-
A_RCOMP
AO
AO
-
-
-
-
Notes:
1 = driven to V_CC
0 = driven to V_SS
X = driven to unknown state
ID = the input is disabled
H = pulled up to V_CC
PD = pull-up disabled
AO = analog output level
L = pulled down to V_SS
Z = output disabled (floats)
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven
VI = Need to drive a Valid Input level
† = After power fail sequence completes
‡ = Caused by Hi-Z from mode pins only
1.
Clocks become valid right before M_RST# deasserts.
2.
ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3.
High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4.
Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5.
Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of
PWRGD.)
May 2005
34
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
Datasheet