80333 Datasheet, PDF (14/75 Pages) Intel Corporation – I/O Processor

80333
2.12
2.13
2.14
Interrupt Controller Unit
The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the
80333 to the Intel XScale^® core processor. The ICU supports high performance interrupt
processing with direct interrupt service routine vector generation on a per source basis. Each source
has programmability for masking, core processor interrupt input, and priority.
GPIO
The 80333 includes eight General Purpose I/O (GPIO) pins which can also be used as external
interrupt inputs.
SMBus Unit
The SMBus (System Management Bus) Interface Unit allows the 80333 to serve as a slave device
on the SMBus. SMBus is based on the principles of the I²C bus and allows the 80333 to interface to
system SMBus for external access and control of internal registers.
May 2005
14
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
Datasheet