80333 Datasheet, PDF (20/75 Pages) Intel Corporation – I/O Processor

80333
Table 7.
B PCI (Slot Expansion) Bus Signals (Sheet 1 of 2)
Name
B_AD[31:0]
B_AD[63:32]
B_PAR
B_PAR64
B_C/BE[7:0]#
B_GNT[4]#
B_GNT[3]#
B_GNT[2]#
B_GNT[1]#
B_GNT[0]#
B_REQ64#
B_REQ[4]#
B_REQ[3]#
B_REQ[2]#/
B_HM66EN
B_REQ[1]#
B_REQ[0]#
B_ACK64#
B_FRAME#
Count
32
32
1
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
Type
Description
I/O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
O
Sync(B)
Rst(B)
O
Sync(B)
Rst(B)
O
Sync(B)
Rst(B)
O
Sync(B)
Rst(B)
O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
I
Sync(B)
I
Sync(B)
I
Sync(B)
I
Sync(B)
I
Sync(B)
I/O
Sync(B)
Rst(B)
I/O
Sync(B)
Rst(B)
B PCI Address/Data is the multiplexed PCI address and lower
32 bits of the data bus.
B PCI Address/Data is the upper 32 bits of the PCI data bus
driven during the data phase.
B PCI Bus Parity is even parity across B_AD[31:0] and
B_C/BE[3:0]#.
B PCI Bus Upper DWORD Parity is even parity across
B_AD[63:32] and B_C/BE[7:4]#.
B PCI Bus Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte enables
for B_AD[63:0].
B Secondary PCI Bus Grant signals sent to device 4 on the B-
segment PCI bus.
B Secondary PCI Bus Grant signals sent to device 3 on the B-
segment PCI bus.
B Secondary PCI Bus Grant signal sent to device 2 on the B-
segment PCI bus.
B Secondary PCI Bus Grant signal sent to device 1 on the B-
segment PCI bus.
B PCI Bus Grant is the grant signal sent to device 0 on the B-
segment PCI bus.
B PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-
bit transaction on the PCI bus. When the target is 64-bit capable,
the target acknowledges the attempt with the assertion of
B_ACK64#.
B PCI Bus Requests is the request signal for device 4 on the B-
segment PCI bus.
B PCI Bus Requests is the request signal for device 3 on the B-
segment PCI bus.
B PCI Bus Requests is the request signal for device 2 on the B-
segment PCI bus.
PCI 66 Enable is used to determine when the slot is PCI 66 MHz
capable. This signal is only valid for Hot-Plug 1-slot mode.
B PCI Bus Requests is the request signal for device 1 on the
B-segment PCI bus.
B PCI Bus Requests are the request signals from device 0 on the
B-segment secondary PCI bus.
B PCI Bus Acknowledge 64-Bit Transfer indicates that the
device has positively decoded its address as the target of the
current access and the target is willing to transfer data using the
full 64-bit data bus.
B PCI Bus Cycle Frame is asserted to indicate the beginning and
duration of an access.
May 2005
20
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
Datasheet