80333 Datasheet, PDF (35/75 Pages) Intel Corporation – I/O Processor

80333
Table 16.
Pin Mode Behavior (Sheet 4 of 4)
Pin
Reset
Norm
ECC
Off
32-Bit
DDR
32-Bit
B_PCI
32-Bit
A_PCI
B_RCOMP
AO
AO
-
-
-
-
XINT[7:4]#
VI
VI
-
-
-
-
XINT[3:0]#
VI
VI
-
-
-
-
HPI#
VI
VI
-
-
-
-
B_HPWRFLT# (5)
VI
VI
-
-
-
-
B_HMRL# (5)
VI
VI
-
-
-
-
B_HPRSNT2# (5)
VI
VI
-
-
-
-
B_HPWREN (5)
Z
VO
-
-
-
-
B_HPRSNT1# (5)
VI
VI
-
-
-
-
B_HATNLED# (5)
Z
VO
-
-
-
-
B_HPWRLED# (5)
Z
VO
-
-
-
-
B_HBUTTON# (5)
VI
VI
-
-
-
-
SCL0, SCD0, SCL1/ SCLK,
SCD1/ SDTA
H
VB
-
-
-
-
GPIO[3:0]/ U0_RTS#, U0_CTS#,
U0_TXD, U0_RXD,
VI
VB
-
-
-
-
GPIO[7:4]/ U1_RTS#, U1_CTS#,
U1_TXD, U1_RXD
VI
VB
-
-
-
-
TCK
VI
VI
-
-
-
-
TDI
TDO
H
H
-
-
-
-
VO^†
VO
-
-
-
-
TRST#
H
H
-
-
-
-
TMS
H
H
-
-
-
-
PWRDELAY
VI
VI
-
-
-
-
PWRGD
VI
VI
-
-
-
-
NC[3:0]
H
H
-
-
-
-
Notes:
1 = driven to V_CC
0 = driven to V_SS
X = driven to unknown state
ID = the input is disabled
H = pulled up to V_CC
PD = pull-up disabled
AO = analog output level
L = pulled down to V_SS
Z = output disabled (floats)
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven
VI = Need to drive a Valid Input level
† = After power fail sequence completes
‡ = Caused by Hi-Z from mode pins only
1.
Clocks become valid right before M_RST# deasserts.
2.
ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3.
High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4.
Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5.
Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of
PWRGD.)
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
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