80333 Datasheet, PDF (33/75 Pages) Intel Corporation – I/O Processor

80333
Table 16.
Pin Mode Behavior (Sheet 2 of 4)
Pin
Reset
Norm
ECC
Off
32-Bit
DDR
32-Bit
B_PCI
32-Bit
A_PCI
POE#
1
VO
-
-
-
-
PWE#
1
VO
-
-
-
-
PCE[1]#
H
VO
-
-
-
-
PCE[0]#
H
VO
-
-
-
-
REFCLK+
REFCLK-
VI
VI
-
-
-
-
PE0Tp[7:0]
PE0Tn[7:0]
Z³
VO
-
-
-
-
PE0Rp[7:0]
PE0Rn[7:0]
ID⁴
VI
-
-
-
-
PE_RCOMPO
VI
VI
PE_ICOMPI
VI
VI
B_AD[63:32]
0
VB
-
-
H
-
B_AD[31:0]
0
VB
-
-
VB
-
B_PAR
0
VB
-
-
VB
-
B_PAR64
Z
VB
-
-
H
-
B_C/BE[7:4]#
0
VB
-
-
H
-
B_C/BE[3:0]#
0
VB
-
-
VB
B_GNT[4:0]#
H
VO
-
-
-
-
B_REQ64#
VO
VB
-
-
-
-
B_REQ[4:0]#
VI
VI
-
-
-
-
B_ACK64#
Z
VB
-
-
-
-
B_FRAME#
Z
VB
-
-
-
-
B_IRDY#
Z
VB
-
-
-
-
B_TRDY#
VO
VB
-
-
-
-
B_STOP#
VO
VB
-
-
-
-
B_DEVSEL#
VO
VB
-
-
-
-
B_LOCK#
Z
VB
-
-
-
-
B_SERR#
Z
VB
-
-
-
-
B_CLKIN
VI
VI
-
-
-
-
PWRGD
VI
VI
-
-
-
-
RSTIN#
VI
VI
-
-
-
-
B_RST#
VO
VO
-
-
-
-
Notes:
1 = driven to V_CC
0 = driven to V_SS
X = driven to unknown state
ID = the input is disabled
H = pulled up to V_CC
PD = pull-up disabled
AO = analog output level
L = pulled down to V_SS
Z = output disabled (floats)
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven
VI = Need to drive a Valid Input level
† = After power fail sequence completes
‡ = Caused by Hi-Z from mode pins only
1.
Clocks become valid right before M_RST# deasserts.
2.
ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3.
High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4.
Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5.
Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of
PWRGD.)
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
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