80333 Datasheet, PDF (66/75 Pages) Intel Corporation – I/O Processor

80333
4.4.6
Table 34.
PCI Express* Differential Transmitter (Tx) Output Specifications
PCI Express* Tx Output Specifications
Symbol
Parameter
Min. Nom. Max. Units Notes
UI
Unit Interval
400
ps
1
V_DIFFp-p Differential output voltage
.800
1.200
V
2
T_rise, T_fall Driver Rise/Fall Time
0.2
0.4
UI
3
V_TX-CM-AC AC Common Mode
20
mV
4
V_{TX-CM-DC Common Mode Active to Sleep mode delta}
-50
delta
+50
mV
RL-Diff_TX Differential Return Loss
15
dB
5
RL-CM_TX Common Mode Return Loss
6
dB
5
Z_TX-OUT-DC DC Differential Output Impedance
90 100 110
Ω
6
Z_TX-Match-DC D+/D- impedance matching
-5
+5
%
7
L_SKEW-TX Lane to Lane Skew at Tx
500
ps
8
J_TOTAL
Total Output Jitter.
0.35
UI
9
T_Deye
Minimum Transmitter eye opening.
0.65
UI
10
I_TX-SHORT Short Circuit Current
-100
100
mA
11
V_TX-IDLE Sleep mode Voltage Output
0
0
20
mV
12
Notes:
1.
±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated
with this value. This UI spec is a ‘before transmission’ specification and represents the nominal time
of each bit transmission or width.
2.
Peak-Peak differential voltage. V_DIFFp-p = 2 × V_DMAx. Specified at the package pins into a 100 Ω test
load as shown in Figure 19, “Transmitter Test Load (100 W differential load)” on page 74. Max level
set by maximum single ended voltage after a reflection from an open. This value is for the first bit after
a transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB
(±0.5 dB) less as measured differentially peak to peak than the specified value.
3.
20–80% at Transmitter. Slower rise/fall times are better.
4.
Peak common mode value. |V_D+ + V_D-|/2 - V_CM-DC(avg).
5.
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels.
The reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω
for common mode (i.e., as measured by a Vector Network Analyzer with 100 Ω differential probes).
Note this is based on a nominal PCI Express* interconnect differential characteristic impedance of
100 Ω. Applicable during active (L0) and Align states only.
6.
DC Differential Mode Impedance 100 Ω ±10% tolerance. All devices shall employ on-chip adaptive
impedance matching circuits to ensure the best possible termination/Zout for its Transmitters (as well
as Receivers).
7.
DC impedance matching between two lanes of a port.
8.
Between any two lanes within a single Transmitter.
9.
Clock source PPM mismatch is in addition to this value. Measured over 250 UI.
10. See Figure 20, “Transmitter Eye Diagram” on page 75.
11. Between any voltage from max supply to gnd with power on or off.
12.
Squelch condition. Both signals brought to V_{CM-DC-|VD+ - VD-|.}
May 2005
66
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
Datasheet