80960CA-33 Datasheet, PDF (63/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
PCLK2:1
ADS
! (BLAST
& READY
& !WAIT)
DACKx
(All Modes)
DREQx
(Case 1)
DREQx
(Case 2)
(See Note)
System
Clock
Start DMA
Bus Request
End of DMA
Bus Request
High To Prevent
Next Bus Cycle
t_IS5 t_IH5
DMA
Acknowledge
High To Prevent
Next Bus Cycle
t_IS5 t_IH5
DMA
Request
Note:
1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and
unpacking modes in which loads are followed by loads or stores are followed by stores.
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
Applications are non Fly-By transfers and adjacent load-stores or store-loads.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
accesses (defined by ADS and BLAST. Refer to i960^® Cx Microprocessor User’s Manual for “access”,
“request” definitions.
Figure 43. DREQ and DACK Functional Timing
F_CX018A
PCLK2:1
EOP
2 CLKs Min
15 CLKs Max
Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
triggered. EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
F_CX045A
Figure 44. EOP Functional Timing
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