80960CA-33 Datasheet, PDF (28/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
Table 16. 80960CA AC Characteristics (33 MHz) (Continued)
(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test
Conditions.)
Symbol
Parameter
Min
Max
Units Notes
Relative Output Timings (1,2,3,8)
T_AVSH1
T_AVSH2
A31:2 Valid to ADS Rising
BE3:0, W/R, SUP, D/C,
DMA, DACK3:0 Valid to ADS Rising
T–4
T–6
T+4
ns
T+6
ns
T_AVEL1
T_AVEL2
A31:2 Valid to DEN Falling
BE3:0, W/R, SUP, INST,
DMA, DACK3:0 Valid to DEN Falling
T–4
T–6
T+4
ns
T+6
ns
T_NLQV
WAIT Falling to Output Data Valid
T_DVNH
Output Data Valid to WAIT Rising
T_NLNH
WAIT Falling to WAIT Rising
T_NHQX Output Data Hold after WAIT Rising
T_EHTV
DT/R Hold after DEN High
T_TVEL
DT/R Valid to DEN Falling
Relative Input Timings (1,2,3)
±4
ns
N*T – 4
N*T + 4 ns
(4)
N*T ± 4
ns
(4)
(N+1)*T–8 (N+1)*T+6 ns
(5)
T/2 – 7
∞
ns
(6)
T/2 – 4
ns
T_IS5
RESET Input Setup (2-x Clock Mode)
6
ns
(13)
T_IH5
RESET Input Hold (2-x Clock Mode)
5
ns
(13)
T_IS6
DREQ3:0 Input Setup
12
ns
(7)
T_IH6
DREQ3:0 Input Hold
7
ns
(7)
T_IS7
XINT7:0, NMI Input Setup
7
ns
(15)
T_IH7
XINT7:0, NMI Input Hold
3
ns
(15)
T_IS8
RESET Input Setup (1-x Clock Mode)
3
ns
(14)
T_IH8
RESET Input Hold (1-x Clock Mode)
T/4 + 1
ns
(14)
NOTES:
1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.
2. See Figure 16 for capacitive derating information for output delays and hold times.
3. See Figure 17 for capacitive derating information for rise and fall times.
4. Where N is the number of N_RAD, N_RDD, N_WAD or N_WDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes
active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.
7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for
proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-
chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.
8. These specifications are guaranteed by the processor.
9. These specifications must be met by the system for proper operation of the processor.
10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for
PCLK2:1 loading.
11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in
reset, the input clock may stop even in 1-x mode.
12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-
cent cycles.
13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the
CLKIN. (See Figure 22.)
14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee
the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.
(See Figure 23.)
15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins
are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-
ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-
tive PCLK2:1 rising edges.
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