80960CA-33 Datasheet, PDF (60/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
PCLK
ADS
A31:4, SUP,
DMA, INST,
D/C, BE3:0,
LOCK
W/R
Quad-Word Write Request
N_WAD = 0, N_WDD = 0, N_WDA = 0
Ready Enabled
Valid
BLAST
DT/R
DEN
READY
BTERM
A3:2
See Note
00
01
10
11
WAIT
D31:0
D0
D1
D2
D3
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal will terminate a bus access if the signal is asserted during
the last (or only) data transfer of the bus access.
Figure 40. Terminating a Burst with BTERM
56
F_CX042A