80960CA-33 Datasheet, PDF (4/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS
PAGE
LIST OF FIGURES (continued)
Figure 39 Using External READY ............................................................................................................... 55
Figure 40 Terminating a Burst with BTERM ............................................................................................... 56
Figure 41 BOFF Functional Timing ............................................................................................................ 57
Figure 42 HOLD Functional Timing ............................................................................................................ 58
Figure 43 DREQ and DACK Functional Timing .......................................................................................... 59
Figure 44 EOP Functional Timing .............................................................................................................. 59
Figure 45 Terminal Count Functional Timing .............................................................................................. 60
Figure 46 FAIL Functional Timing ............................................................................................................... 60
Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61
Figure 48 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62
Figure 49 Idle Bus Operation ...................................................................................................................... 63
LIST OF TABLES
Table 1
80960CA Instruction Set .............................................................................................................. 3
Table 2
Pin Description Nomenclature ...................................................................................................... 4
Table 3
80960CA Pin Description — External Bus Signals ...................................................................... 5
Table 4
80960CA Pin Description — Processor Control Signals .............................................................. 8
Table 5
80960CA Pin Description — DMA and Interrupt Unit Control Signals ....................................... 10
Table 6
80960CA PGA Pinout — In Signal Order ................................................................................... 11
Table 7
80960CA PGA Pinout — In Pin Order ........................................................................................ 12
Table 8
80960CA PQFP Pinout — In Signal Order ................................................................................. 15
Table 9
Table 10
Table 11
80960CA PQFP Pinout — In Pin Order ..................................................................................... 16
Maximum T_A at Various Airflows in ^oC (PGA Package Only) ..................................................... 18
80960CA PGA Package Thermal Characteristics ...................................................................... 19
Table 12 80960CA PQFP Package Thermal Characteristics .................................................................... 19
Table 13 Die Stepping Cross Reference ................................................................................................... 20
Table 14 Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21
Table 15 DC Characteristics ..................................................................................................................... 22
Table 16 80960CA AC Characteristics (33 MHz) ...................................................................................... 23
Table 17 80960CA AC Characteristics (25 MHz) ...................................................................................... 25
Table 18 80960CA AC Characteristics (16 MHz) ...................................................................................... 27
Table 19 Reset Conditions ........................................................................................................................ 35
Table 20 Hold Acknowledge and Backoff Conditions ................................................................................ 35
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