80960CA-33 Datasheet, PDF (56/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
Function
Byte
Order
Bus
Width
N_WDD
N_WAD
N_XDA
N_RDD
N_RAD
Pipe- ^External
Lining
Ready
Control
Burst
Bit _31-23
22
21
20-19 18-17 16-12 11-10
9-8
7-3
2
1
0
Value
0
0..0
X
x
0
32-bit
X
X
X
0
10
xx
xxxxx
xx
1
2
ON Disabled Enabled
01
00010
1
0
1
PCLK
A2 1
D
1 D 1 D 1 A' 2
1
D'
D
ADS
A31:4, SUP,
DMA, D/C,
BE3:0, LOCK
W/R
A3:2
D31:0
WAIT
BLAST
DT/R
Valid
Valid
In-
valid
In-
valid
00
01
10
11
Valid
In-
valid
IN
IN
IN
IN
IN
D
D
D
D
D'
DEN
Non-pipelined request concludes,
pipelined reads begin.
Pipelined reads conclude,
Non-pipelined requests begin.
Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus
52
F_CX038A