80960CA-33 Datasheet, PDF (6/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
2.1 The C-Series Core
The C-Series core is a very high performance
microarchitectural implementation of the 80960 Core
Architecture. The C-Series core can sustain execu-
tion of two instructions per clock (66 MIPs at
33 MHz). To achieve this level of performance, Intel
has incorporated state-of-the-art silicon technology
and innovative microarchitectural constructs into the
implementation of the C-Series core. Factors that
contribute to the core’s performance include:
• Parallel instruction decoding allows issuance of
up to three instructions per clock
• Single-clock execution of most instructions
• Parallel instruction decode allows sustained,
simultaneous execution of two single-clock
instructions every clock cycle
• Efficient instruction pipeline minimizes pipeline
break losses
• Register and resource scoreboarding allow simul-
taneous multi-clock instruction execution
• Branch look-ahead and prediction allows many
branches to execute with no pipeline break
• Local Register Cache integrated on-chip caches
Call/Return context
• Two-way set associative, 1 Kbyte integrated
instruction cache
• 1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle
2.2 Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CA to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 132 Mbytes per second (at 33 MHz). Inter-
nally programmable wait states and 16 separately
configurable memory regions allow the processor to
interface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus Controller’s main features
include:
• Demultiplexed, Burst Bus to exploit most efficient
DRAM access modes
• Address Pipelining to reduce memory cost while
maintaining performance
• 32-, 16- and 8-bit modes for I/O interfacing ease
• Full internal wait state generation to reduce
system cost
• Little and Big Endian support to ease application
development
• Unaligned access support for code portability
• Three-deep request queue to decouple the bus
from the core
2.3 Flexible DMA Controller
A four-channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disas-
sembly and a high performance fly-by mode capable
of transfer speeds of up to 59 Mbytes per second at
33 MHz. The DMA controller features a performance
and flexibility which is only possible by integrating the
DMA controller and the 80960CA core.
2.4 Priority Interrupt Controller
A programmable-priority interrupt controller
manages up to 248 external sources through the 8-
bit external interrupt port. The Interrupt Unit also
handles the four internal sources from the DMA
controller and a single non-maskable interrupt input.
The 8-bit interrupt port can also be configured to
provide individual interrupt sources that are level or
edge triggered.
Interrupts in the 80960CA are prioritized and
signaled within 270 ns of the request. If the interrupt
is of higher priority than the processor priority, the
context switch to the interrupt routine typically is
complete in another 480 ns. The interrupt unit
provides the mechanism for the low latency and high
throughput interrupt service which is essential for
embedded applications.
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