80960CA-33 Datasheet, PDF (10/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
Name
READY
BTERM
WAIT
BLAST
DT/R
DEN
LOCK
HOLD
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 2 of 3)
Type
I
S(L)
H(Z)
R(Z)
I
S(L)
H(Z)
R(Z)
O
S
H(Z)
R(1)
O
S
H(Z)
R(0)
O
S
H(Z)
R(0)
O
S
H(Z)
R(1)
O
S
H(Z)
R(1)
I
S(L)
H(Z)
R(Z)
Description
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. If READY is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY pin is deasserted, wait states
continue to be inserted until READY becomes asserted. This is true for the N_RAD,
N_RDD, N_WAD and N_WDD wait states. The N_XDA wait states cannot be extended.
BURST TERMINATE is an input which breaks up a burst access and causes another
address cycle to occur. The BTERM signal works in conjunction with the internally
programmed wait-state generator. If READY and BTERM are enabled in a region, the
BTERM pin is sampled after the programmed number of wait states has expired.
When BTERM is asserted, a new ADS signal is generated and the access is
completed. The READY input is ignored when BTERM is asserted. BTERM must be
externally synchronized to satisfy BTERM setup and hold times.
WAIT indicates internal wait state generator status. WAIT is asserted when wait
states are being caused by the internal wait state generator and not by the READY or
BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be
thought of as a READY output that the processor provides when it is inserting wait
states.
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the wait state counter reaches
zero. BLAST remains asserted until the clock following the last cycle of the last data
transfer of a bus access. If the READY or BTERM input is used to extend wait states,
the BLAST signal remains asserted until READY or BTERM terminates the access.
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in
conjunction with DEN to provide control for data transceivers attached to the external
bus. When DT/R is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R changes only while
DEN is high.
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle.
DEN is used in conjunction with DT/R to provide control for data transceivers attached
to the external bus. DEN remains asserted for sequential reads from pipelined
memory regions. DEN is deasserted when DT/R changes.
BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK
may be used to prevent external agents from accessing memory which is currently
involved in an atomic operation. LOCK is asserted in the first clock of an atomic
operation and deasserted in the clock cycle following the last bus access for the
atomic operation. To allow the most flexibility for memory system enforcement of
locked accesses, the processor acknowledges a bus hold request when LOCK is
asserted. The processor performs DMA transfers while LOCK is active.
HOLD REQUEST signals that an external agent requests access to the external bus.
The processor asserts HOLDA after completing the current bus request. HOLD,
HOLDA and BREQ are used together to arbitrate access to the processor’s external
bus by external bus agents.
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