80960CA-33 Datasheet, PDF(39/68 Page) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

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80960CA-33 Datasheet, PDF (39/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

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80960CA-33, -25, -16

5.0 RESET, BACKOFF AND HOLD

ACKNOWLEDGE

Table 19 lists the condition of each processor output

pin while RESET is asserted (low).

Table 19. Reset Conditions

Pins

State During Reset

(HOLDA inactive)1

A31:2

Floating

D31:0

Floating

BE3:0

Driven high (Inactive)

W/R

Driven low (Read)

ADS

Driven high (Inactive)

WAIT

Driven high (Inactive)

BLAST

Driven low (Active)

DT/R

Driven low (Receive)

DEN

Driven high (Inactive)

LOCK

Driven high (Inactive)

BREQ

Driven low (Inactive)

D/C

Floating

DMA

Floating

SUP

Floating

FAIL

Driven low (Active)

DACK3:0

Driven high (Inactive)

EOP3:0/TC3:0 Floating (Set to input mode)

NOTES:

1. With regard to bus output pin state only, the Hold

Acknowledge state takes precedence over the reset

state. Although asserting the RESET pin will internally

reset the processor, the processorâs bus output pins

will not enter the reset state if it has granted Hold

Acknowledge to a previous HOLD request (HOLDA is

active). Furthermore, the processor will grant new

HOLD requests and enter the Hold Acknowledge state

even while in reset.

For example, if HOLDA is inactive and the processor is

in the reset state, then HOLD is asserted, the proces-

sorâs bus pins enter the Hold Acknowledge state and

HOLDA is granted. The processor will not be able to

perform memory accesses until the HOLD request is

removed, even if the RESET pin is brought high. This

operation is provided to simplify boot-up synchroniza-

tion among multiple processors sharing the same bus.

Table 20 lists the condition of each processor output

pin while HOLDA is asserted (low).

Table 20. Hold Acknowledge

and Backoff Conditions

Pins

A31:2

D31:0

BE3:0

W/R

ADS

WAIT

BLAST

DT/R

DEN

LOCK

BREQ

D/C

DMA

SUP

FAIL

DACK3:0

EOP3:0/TC3:0

State During HOLDA

Floating

Driven (High or low)

Floating

Driven high (Inactive)

Driven (If output)

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