80960CA-33 Datasheet, PDF (3/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS
PAGE
LIST OF FIGURES
Figure 1 80960CA Block Diagram .............................................................................................................. 1
Figure 2 80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13
Figure 3 80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14
Figure 4 80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Figure 5 Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Figure 6 Register g0 ................................................................................................................................. 20
Figure 7 AC Test Load .............................................................................................................................. 29
Figure 8 Input and Output Clocks Waveform ............................................................................................ 29
Figure 9 CLKIN Waveform ........................................................................................................................ 29
Figure 10 Output Delay and Float Waveform ............................................................................................. 30
Figure 11 Input Setup and Hold Waveform ................................................................................................ 30
Figure 12 NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Figure 13 Hold Acknowledge Timings ........................................................................................................ 31
Figure 14 Bus Backoff (BOFF) Timings ...................................................................................................... 32
Figure 15 Relative Timings Waveforms ...................................................................................................... 33
Figure 16 Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Figure 17
Figure 18
Figure 19
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V_CC .................. 34
I_CC vs. Frequency and Temperature ........................................................................................... 34
Cold Reset Waveform ................................................................................................................ 36
Figure 20 Warm Reset Waveform .............................................................................................................. 37
Figure 21 Entering the ONCE State ........................................................................................................... 38
Figure 22 Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Figure 23 Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Figure 24 Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Figure 25 Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Figure 26 Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Figure 27 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Figure 28 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Figure 29 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Figure 30 Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Figure 31 Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Figure 32 Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Figure 33 Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Figure 34 Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Figure 35 Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Figure 36 Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Figure 37 Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Figure 38 Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
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