80960CA-33 Datasheet, PDF (25/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature ................................–65^oC to +150^oC
Case Temperature Under Bias .................–65^oC to +110^oC
Supply Voltage wrt. V_SS ............................. –0.5V to + 6.5V
Voltage on Other Pins wrt. V_SS ...........–0.5V to V_CC + 0.5V
4.2 Operating Conditions
NOTICE: This is a production data sheet. The
specifications are subject to change without notice.
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause perma-
nent damage. These are stress ratings only. Opera-
tion beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
Table 14. Operating Conditions (80960CA-33, -25, -16)
Symbol
Parameter
Min Max Units Notes
V_CC
Supply Voltage
80960CA-33 4.75 5.25
V
80960CA-25 4.50 5.50
V
80960CA-16 4.50 5.50
V
f_CLK2x
Input Clock Frequency (2-x Mode)
80960CA-33
0
66.66 MHz
80960CA-25
0
50
MHz
80960CA-16
0
32
MHz
f_CLK1x
Input Clock Frequency (1-x Mode)
T_C
Case Temperature Under Bias
80960CA-33, -25, -16
80960CA-33
8
33.33 MHz
80960CA-25
8
25
MHz
(1)
80960CA-16
8
16
MHz
PGA Package
0
100
o_C
196-Pin PQFP
0
100
o_C
NOTES:
1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum fre-
quency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the pro-
cessor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once
CLKIN restarts and has stabilized.
4.3 Recommended Connections
Power and ground connections must be made to
multiple V_CC and V_SS (GND) pins. Every 80960CA-
based circuit board should include power (V_CC) and
ground (V_SS) planes for power distribution. Every
V_CC pin must be connected to the power plane, and
every V_SS pin must be connected to the ground
plane. Pins identified as “NC” must not be
connected in the system.
Liberal decoupling capacitance should be placed
near the 80960CA. The processor can cause tran-
sient power surges when its numerous output buffers
transition, particularly when connected to large
capacitive loads.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance can be reduced by short-
ening the board traces between the processor and
decoupling capacitors as much as possible. Capaci-
tors specifically designed for PGA packages will offer
the lowest possible inductance.
For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, any
unused interrupt (XINT, NMI) or DMA (DREQ) input
should be connected to V_CC through a pull-up
resistor, as should BTERM if not used. Pull-up resis-
tors should be in the in the range of 20 KΩ for each
pin tied high. If READY or HOLD are not used, the
unused input should be connected to ground. N.C.
pins must always remain unconnected. Refer to
the i960^® Cx Microprocessor User’s Manual (Order
Number 270710) for more information.
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