80960CA-33 Datasheet, PDF (5/68 Pages) Intel Corporation – 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

80960CA-33, -25, -16
1.0 PURPOSE
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic—other than parametric performance—consult
the 80960CA Product Overview (Order No. 270669)
or the i960^® CA Microprocessor User’s Manual
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel’s FaxBACK^® data-on-
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600).
2.0 80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory sub-system. In
addition, the 80960CA’s on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system’s
slower, cost sensitive, main memory subsystem.
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers—in
addition to source or destination synchronized trans-
fers—are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (”latency”) time of
750 ns.
Interrupt _Programmable
Port ^{Interrupt Controller}
Multiply/Divide
Unit
Execution
Unit
Instruction Prefetch Queue
Instruction Cache
(1 KByte, Two-way
Set Associative)
128-BIT CACHE BUS
Parallel
Instruction
Scheduler
Register-side
Machine Bus
Memory-side
Machine Bus
Four-Channel ^DMA
DMA Controller Port
Memory Region
Configuration
Bus
Controller
Bus Request
Queues
Control
Address
Data
1 KByte
Data RAM
5 to 15 Sets
Register Cache
Six-port
Register File
64-Bit
SRC1 Bus
32-Bit
Base Bus
Address
Generation Unit
64-Bit
SRC2 Bus
128-Bit
Load Bus
64-Bit
DST Bus
128-Bit
Store Bus
Figure 1. 80960CA Block Diagram
F_CX001A
1