IA8044_10 Datasheet, PDF (50/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
5. AC Specifications
AC characteristics, external data memory characteristics, serial interface characteristics, and
external clock drive characteristics are provided in Tables 48 through 51, respectively.
TA ^{= −40 C to +85 C, VDD = 5V 10%, VSS = 0V, Load Capacitance = 87pF}
Table 48. External Program Memory Characteristics
Variable Clock
12 MHz Osc 1/TCLCL = 3.5 MHz to 12 MHz
Symbol
Parameter
Min Max
Min
Max
Unit
TLHLL ALE Pulse Width
171 –
2TCLCL+4
–
ns
TAVLL Address Valid to ALE Low
75 –
TCLCL-8
–
ns
TLLAX Address Hold After ALE Low 74 –
TCLCL-9
–
ns
TLLIV ALE Low to Valid Instr. In.
– 298
–
4TCLCL-35 ns
TLLPL ALE Low to PSENn Low
83 –
TCLCL
–
ns
TPLPH PSENn Pulse Width
254 –
3TCLCL+4
–
ns
TPLIV PSENn Low to Valid Instr. In – 215
–
3TCLCL-35 ns
TPXIX Input Instr. Hold After PSENn 0
–
0
–
ns
TPXIZ Input Instr. Float After PSENn – 76
–
TCLCL-7 ns
TPXAV PSENn to Address Valid
91 –
TCLCL+8
–
ns
TAVIV Address to Valid Instr. In
– 373
–
5TCLCL-43 ns
TAZPL Address Float to PSENn
-9
–
-9
–
ns
TCY Machine cycle
996 –
12TCLCL
–
ns
Table 49. External Data Memory Characteristics
Symbol
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
Parameter
RDn Pulse Width
WRn Pulse Width
Address Hold After ALE
RDn Low to Valid Data In
Data Hold After RDn
Data Float After RDn
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transition
Data Setup Before WRn High
Data Held After WRn
Variable Clock
12 MHz Osc 1/TCLCL = 3.5 MHz to 12 MHz
Min Max
Min
Max
Unit
487 –
6TCLCL-13
–
ns
487 –
6TCLCL-13
–
ns
74 –
TCLCL-9
–
ns
– 383
–
5TCLCL-35 ns
0
–
0
–
ns
– 165
–
2TCLCL-2 ns
– 633
–
8TCLCL-34 ns
– 708
–
9TCLCL-42 ns
250 250
3TCLCL
3TCLCL ns
325 –
4TCLCL-8
–
ns
76 –
TCLCL-7
–
ns
563 –
7TCLCL-20
–
ns
86 –
TCLCL+3
–
ns
®
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