IA8044_10 Datasheet, PDF (22/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
4.3.4 Bit Addressable Memory
Both the internal RAM and the SFRs have locations that are bit addressable in addition to the byte
addressable locations (see Tables 7 and 8).
Table 7. SFR Bit Addressable Locations
Byte Address
F0h
E0h
D8h
D0h
C8h
B8h
B0h
A8h
A0h
90h
88h
80h
Bit [7]
F7h
E7h
DFh
D7h
CFh
–
B7h
AFh
A7h
97h
8Fh
87h
Bit [6]
F6h
E6h
DEh
D6h
CEh
–
B6h
–
A6h
96h
8Eh
86h
Bit [5]
F5h
E5h
DDh
D5h
CDh
–
B5h
–
A5h
95h
8Dh
85h
Bit [4]
F4h
E4h
DCh
D4h
CCh
BCh
B4h
ACh
A4h
94h
8Ch
84h
Bit [3]
F3h
E3h
DBh
D3h
CBh
BBh
B3h
ABh
A3h
93h
8Bh
83h
Bit [2]
F2h
E2h
DAh
D2h
CAh
BAh
B2h
AAh
A2h
92h
8Ah
82h
Bit [1]
F1h
E1h
D9h
D1h
C9h
B9h
B1h
A9h
A1h
91h
89h
81h
Bit [0]
F0h
E0h
D8h
D0h
C8h
B8h
B0h
A8h
A0h
90h
88h
80h
Register
B
ACC
NSNR
PSW
STS
IP
P3
IE
P2
P1
TCON
P0
Table 8. Internal RAM Bit Addressable Locations
Byte Address
30h-BFh
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Bit [7] Bit [6] Bit [5] Bit [4]
Upper Internal RAM Locations
7Fh 7Eh 7Dh 7Ch
77h 76h 75h 74h
6Fh 6Eh 6Dh 6Ch
67h 66h 65h 64h
5Fh 5Eh 5Dh 5Ch
57h 56h 55h 54h
4Fh 4Eh 4Dh 4Ch
47h 46h 45h 44h
3Fh 3Eh 3Dh 3Ch
37h 36h 35h 34h
2Fh 2Eh 2Dh 2Ch
27h 26h 25h 24h
1Fh 1Eh 1Dh 1Ch
17h 16h 15h 14h
0Fh 0Eh 0Dh 0Ch
07h 06h 05h 04h
Register Bank 3
Register Bank 2
Register Bank 1
Register Bank 0
Bit [3]
7Bh
73h
6Bh
63h
5Bh
53h
4Bh
43h
3Bh
33h
2Bh
23h
1Bh
13h
0Bh
03h
Bit [2]
7Ah
72h
6Ah
62h
5Ah
52h
4Ah
42h
3Ah
32h
2Ah
22h
1Ah
12h
0Ah
02h
Bit [1]
79h
71h
69h
61h
59h
51h
49h
41h
39h
31h
29h
21h
19h
11h
09h
01h
Bit [0]
78h
70h
68h
60h
58h
50h
48h
40h
38h
30h
28h
20h
18h
10h
08h
00h
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