IA8044_10 Datasheet, PDF (29/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Bit [2]—IT1→ (TCON.2) Interrupt 1 type control bit. Selects falling edge or low level on
input pin to cause interrupt.
Bit [1]—IE0→ (TCON.1) Interrupt 0 edge flag. Set by hardware, when falling edge on
external pin INT1 is observed. Cleared when interrupt is processed.
Bit [0]—IT0→ (TCON.0) Interrupt 0 type control bit. Selects falling edge or low level on
input pin to cause interrupt.
4.7.8 Timer 0 High Byte (TH0)
Table 18 presents the high-order byte of Timer/Counter 0.
Table 18. Timer 0 High Byte Register
7
6
5
4
3
2
1
0
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
4.7.9 Timer 0 Low Byte (TL0)
Table 19 presents the low-order byte of Timer/Counter 0.
Table 19. Timer 0 Low Byte Register
7
6
5
4
3
2
1
0
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
4.7.10 Timer 1 High Byte (TH1)
Table 20 presents the high-order byte of Timer/Counter 1.
Table 20. Timer 1 High Byte Register
7
6
5
4
3
2
1
0
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
4.7.11 Timer 1 Low Byte (TL1)
Table 21 presents the low order byte of Timer/Counter 1.
Table 21. Timer 1 Low Byte Register
7
6
5
4
3
2
1
0
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
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