IA8044_10 Datasheet, PDF (35/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
4.9.5 Interrupt Handling
The interrupt flags are sampled during each machine cycle. The samples are polled during the
next machine cycle. If an interrupt flag is captured, the interrupt system will generate an LCALL
instruction to the appropriate service routine, provided that this is not disabled by the following
conditions:
An interrupt of the same or higher priority is processed.
The current machine cycle is not the last cycle of the instruction (the instruction cannot be
interrupted).
The instruction in progress is RETI or any write to IE or IP registers.
Note: If an interrupt is disabled and the interrupt flag is cleared before the
blocking condition is removed, no interrupt will be generated because the
polling cycle will not sample any active interrupt condition. In other words,
the interrupt condition is not remembered; every polling cycle is new.
4.9.6 Interrupt Priority Register (IP)
This register sets the interrupt priority to high or low for each interrupt. When the bit is set, it
selects high priority. Within each level the interrupts are prioritized as follows:
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
SIU
An interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority (see
Table 29).
Table 29. Interrupt Priority Register
765 4 3 2 1 0
– – – PS PT1 PX1 PT0 PX0
Bit [7]—(IP.7)
Bit [6]—(IP.6)
Bit [5]—(IP.5)
Bit [4]—PS → (IP.4) SIU interrupt priority bit
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