IA8044_10 Datasheet, PDF (47/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Int clk
T1 ovrflw
SCLK
RXD
TXD
div by 2
Bit Processor
DPLL
Bit timing
generator
zero insert/
delete
NRZI encode/
decode
serial/parallel
shifter
start detect
FCS
generator/
checker
Byte Processor
Control State
Machine
Decision
Logic
Serial Information Bus
Internal Ram
SIU SFRs
Figure 11. Bit and Byte Processors
Information Bus
®
IA211010112-04
UNCONTROLLED WHEN PRINTED OR COPIED
Page 47 of 65
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