IA8044_10 Datasheet, PDF (46/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Frame Option NFCS NB AM
No-Control
1
1 1 Fl
Ad
Field
No-FCS Field
FLEXIBLE
Mode
No-Control
1
1 0 Fl
Inf
Field
No-Address
Field
No-FCS Field
FLEXIBLE
Mode
Ad = Address field
Co = Control field
FCS = Frame check sequence
Fl = Flag
Inf = Information field
Frame Format
Inf
Fl
Fl
4.14 HDLC Restrictions
The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the
restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast, HDLC
allows for any number of bits in the information field. HDLC provides an unlimited address field
and an extended frame number sequencing. HDLC does not support loop configuration.
4.15 SIU Details
The SIU is composed of two functional blocks with each having several sub blocks. The two
blocks are called the bit processor (BIP) and the byte processor (BYP) (see Figure 11).
4.15.1 BIP
The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero
insertion/deletion, shutoff logic, and FCS generation/checking. The NRZI logic compares the
current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts
the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete
circuitry inserts and deletes zeros and also detects flags (01111110), go-aheads (GA) (01111111),
and aborts (1111111). The pattern 1111110 is detected as an early go-ahead that can be turned
into a flag in loop configurations. The shutoff detector is a three-bit counter that is used to detect
a sequence of eight zeros, which is the shutoff command in loop-mode transmissions. It is cleared
whenever a ―1‖ is detected. The FCS logic performs the generation and checking of the FCS
value according to the polynomial described above. The FCS register is set to all 1s prior to each
calculation. If a CRC error is generated on a receive frame, the SIU will not interrupt the CPU
and the error will be cleared upon receiving an opening flag.
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