IA8044_10 Datasheet, PDF (33/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Bit [2]—OV → (PSW.7) Overflow flag
Bit [1]—(PSW.7) User defined flag
Bit [0]—P → (PSW.7) Parity flag, affected by hardware to indicate odd/even number of
―one‖ bits in the Accumulator (i.e., even parity)
The state of Bits RS1 and RS0 selects the working registers bank as presented in Table 25.
Table 25. RS1/RS0 Bank Selections by State
RS1/RS0
00
01
10
11
Bank selected location
Bank 0 (00H–07H)
Bank 1 (08H–0FH)
Bank 2 (10H–17H)
Bank 3 (18H–1FH)
4.8.4 Stack Pointer (SP)
Table 26 presents the stack pointer, which is a 1-byte register initialized to 07H after reset. This
register is incremented before PUSH and CALL instructions, causing the stack to begin at location
08H. The stack pointer points to a location in internal RAM.
Table 26. Stack Pointer
7
6
5
4
3
2
1
0
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
4.8.5 Data Pointer (DPTR)
The data pointer (DPTR) is two bytes wide. Table 27 presents the highest, which is DPH.
Table 28 presents the lower part, DPL. It can be loaded as a 2-byte register (MOV
DPTR,#data16) or as two registers (MOV DPL,#data8 each). It is generally used to access
external code (MOVC A,@A+DPTR each) or data space (MOV A,@DPTR).
Table 27. Data Pointer (High) Register
7
6
5
4
3
2
1
0
DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
Table 28. Data Pointer (Low) Register
7
6
5
4
3
2
1
0
DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
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