IA8044_10 Datasheet, PDF (42/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Table 42. Receive Control Byte Register
7
6
5
4
3
2
1
0
RCB.7 RCB.6 RCB.5 RCB.4 RCB.3 RCB.2 RCB.1 RCB.0
4.10.13 DMA Count Register (DMA CNT)
Table 43 presents the DMA Count Register (DMA CNT), which contains the number of bytes
remaining for the information field currently being used. This register is an ICE support register.
DMA CNT is byte addressable.
Table 43. DMA Count Register (DMA CNT)
7
6
5
4
3
2
1
0
DMA DMA DMA DMA DMA DMA DMA DMA
CNT.7 CNT.6 CNT.5 CNT.4 CNT.3 CNT.2 CNT.1 CNT.0
4.10.14 DMA Count Register (FIFO)
Table 44 presents the DMA Count Register (FIFO), which is actually three registers that make a
three-byte FIFO. These are used as temporary storage between the eight-bit shift register and the
receive buffer when an information field is received. This register is an ICE support register.
FIFO is byte addressable.
Table 44. DMA Count Register (FIFO)
7
6
5
4
3
2
1
0
FIFO#^a.7 FIFO#^a.6 FIFO#^a.5 FIFO#^a.4 FIFO#^a.3 FIFO#^a.2 FIFO#^a.1 FIFO#^a.0
a_{1, 2, or 3 for FIFO1, FIFO2, or FIFO3, respectively.}
4.10.15 SIU State Counter (SIUST)
Table 45 presents the SIU State Counter Register, which indicates what state the SIU state
machine is currently in. This in turn indicates what task the SIU is performing or which field is
expected next by the SIU. This register should not be written to. This register is an ICE support
register. SIUST is byte addressable.
Table 45. SIU State Counter
7
6
5
4
3
2
1
0
SIUST .7 SIUST .6 SIUST .5 SIUST .4 SIUST .3 SIUST .2 SIUST .1 SIUST .0
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