IA8044_10 Datasheet, PDF (34/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
4.9 Interrupts
The IA8044/IA8344 provides five interrupt sources. There are two external interrupts accessible
through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are also
internal interrupts associated with Timer 0 and Timer 1 and an internal interrupt from the SIU.
4.9.1 External Interrupts
The choice between external interrupt level or transition activity is made by setting IT1 and IT0
bits in the SFR TCON. When the interrupt event happens, a corresponding Interrupt Control Bit is
set (IT0 or IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled.
When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1) is
cleared, provided that the edge triggered mode was selected. If level mode is active, the external
requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1 (0 or 1).
4.9.2 Timer 0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the rollover of
Timers 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is
cleared by the hardware if the CPU accessed the corresponding interrupt service vector. This can
be done only if this interrupt is enabled in the IE register.
4.9.3 Serial Interface Unit Interrupt
The SIU generates an interrupt when a frame is received or transmitted. No interrupts are
generated for a received frame with errors.
4.9.4 Interrupt Priority Level Structure
There are two priority levels in the IA8044/IA8344—any interrupt can be individually
programmed to a high or low priority level. Modifying the appropriate bits in the SFR IP can
accomplish this. A low-priority interrupt service routine will be interrupted by a high-priority
interrupt. However, the high-priority interrupt cannot be interrupted.
If two interrupts of the same priority level occur, an internal polling sequence determines which
will be processed first. This polling sequence is a second priority structure defined as follows:
IE0 1—highest
TF0 2
IE1 3
TF1 4
SIU—lowest
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