IA8044_10 Datasheet, PDF (37/65 Pages) InnovASIC, Inc – SDLC Communications Controller

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
three serial data link configurations, 1) half-duplex, point-to-point, 2) half-duplex, multipoint,
or 3) loop mode.
4.10.1 SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via 11 SFRs. The Serial Interface
Unit Control Registers are detailed in the sections that follow.
4.10.2 Serial Mode Register (SMD)
Table 31 presents the serial mode register, which sets the operational mode of the SIU. The CPU
can read and write SMD. The SIU can read SMD. To prevent conflicts between CPU and SIU,
accesses to SMD the CPU should write SMD only when RTS and RBE bits in the STS register are
both zero. SMD is normally only accessed during initialization. This register is byte addressable.
Table 32 presents the serial mode select clock mode bits.
Table 31. Serial Mode Register
7
6
5
4
3
21
0
SCM2 SCM1 SCM0 NRZI LOOP PFS NB NFCS
Bit [7]—SCM2 → (SMD.7) Select clock mode—Bit [2].
Bit [6]—SCM1 → (SMD.6) Select clock mode—Bit [1].
Bit [5]—SCM0 → (SMD.5) Select clock mode—Bit [0].
Bit [4]—NRZI → (SMD.4) When set selects NRZI encoding otherwise NRZ.
Bit [3]—LOOP → (SMD.3) When set, selects loop configuration, else point-to-point
mode.
Bit [2]—PFS → (SMD.2) Pre-frame sync mode. When set, causes two bytes to be
transmitted before the first flag of the frame for DPLL synchronization. If NRZI is set,
00H is transmitted, otherwise 55H. This ensures that 16 transitions are sent before the
opening flag.
Bit [1]—NB → (SMD.1) Non-buffered mode. No control field contained in SDLC frame.
Bit [0]—NFCS → (SMD.0) When set, selects No FCS field contained in the SDLC frame.
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