HYB18L256160BF Datasheet, PDF (9/49 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Overview
1.3
Description
The HY[B/E]18L256160B[C/F] is a high-speed CMOS, dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L256160B[C/F] achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L256160B[C/F] is especially designed for mobile applications. It operates from a 1.8V power
supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor
(OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-
Down (DPD) mode.
The HY[B/E]18L256160B[C/F] is housed in a 54-ball P-VFBGA package. It is available in Commercial (0 °C to
70 °C) and Extended (-25 °C to +85 °C) temperature range.
CKE
CLK
CS
RAS
CAS
WE
Mode
Registers
13
13
A0-A12
BA0,BA1
15
2
2
9
Column Address
Counter / Latch
Figure 2 Functional Block Diagram
Bank 3
Bank 2
Bank 1
8192
Bank 0
Memory Array
(8192 x 512 x 16)
Sense Amplifier
IO Gating
DQM Mask Logic
2
2
Data
Output
Reg.
16
16
Data
Input
Reg.
LDQM
UDQM
DQ0-
DQ15
Column
9
Decoder
Data Sheet
9
V1.4, 2004-04-30