HYB18L256160BF Datasheet, PDF (22/49 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
Table 10 Timing Parameters for READ
Parameter
Symbol
- 7.5
Units
min.
max.
Access time from CLK
CL = 3
t_AC
–
CL = 2
t_AC
–
DQ low-impedance time from CLK
t_LZ
1.0
DQ high-impedance time from CLK
t_HZ
3.0
Data out hold time
t_OH
2.5
DQM to DQ High-Z delay (READ Commands)
t_DQZ
–
ACTIVE to ACTIVE command period
t_RC
67
ACTIVE to READ or WRITE delay
t_RCD
19
ACTIVE to PRECHARGE command period
t_RAS
45
PRECHARGE command period
t_RP
19
5.4
ns
6.0
ns
–
ns
7.0
ns
–
ns
2
t_CK
–
ns
–
ns
100k
ns
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
–
–
–
–
1)
1)
1)
1)
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
CLK
Command
Address
ACT
Ba A,
Row x
A10 (AP) Row x
DQ
t_RCD
NOP
t_RAS
t_RC
READ
NOP
NOP
NOP
PRE
t_RP
NOP
ACT
Ba A,
Col n
Dis AP
CL=2
Pre All
AP
Pre Bank A
Ba A,
Row b
Row b
DO n
DO n+1 DO n+2 DO n+3
Ba A, Col n = bank A, column n
AP = Auto Precharge
DO n = Data Out from column n
Dis AP = Disable Auto Precharge
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 13 Single READ Burst (CAS Latency = 2)
= Don't Care
Data Sheet
22
V1.4, 2004-04-30