HYB18L256160BF Datasheet, PDF (7/49 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Overview
1
Overview
1.1
Features
• 4 banks × 4 Mbit × 16 organization
• Fully synchronous to positive clock edge
• Four internal banks for concurrent operation
• Programmable CAS latency: 2, 3
• Programmable burst length: 1, 2, 4, 8 or full page
• Programmable wrap sequence: sequential or interleaved
• Programmable drive strength
• Auto refresh and self refresh modes
• 8192 refresh cycles / 64 ms
• Auto precharge
• Commerical (0°C to +70°C) and Extended (-25^oC to +85^oC) operating temperature range
• 54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
• Low supply voltages: V_DD = 1.8 V ± 0.15 V, V_DDQ = 1.8 V ± 0.15 V
• Optimized self refresh (I_DD6) and standby currents (I_DD2/I_DD3)
• Programmable Partial Array Self Refresh (PASR)
• Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
• Power-Down and Deep Power Down modes
Table 1 Performance
Part Number Speed Code
Speed Grade
Access Time (t_ACmax)
Clock Cycle Time (t_CKmin)
CL = 3
CL = 2
CL = 3
CL = 2
- 7.5
133
5.4
6.0
7.5
9.5
Unit
MHz
ns
ns
ns
ns
Table 2
Item
Banks
Rows
Columns
Memory Addressing Scheme
Addresses
BA0, BA1
A0 - A12
A0 - A8
Data Sheet
7
V1.4, 2004-04-30