HYB18L256160BF Datasheet, PDF (28/49 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

2.4.6 WRITE
CLK
CKE
CS
RAS
CAS
WE
A0-A8
A10
BA0,BA1
(High)
CA
Enable AP
AP
Disable AP
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Figure 23 WRITE Command
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
WRITE bursts are initiated with a WRITE command, as
shown in Figure 23. Basic timings for the DQs are
shown in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided
with the WRITE command, and Auto Precharge is
either enabled or disabled for that access. If Auto
Precharge is enabled, the row being accessed is
precharged at the completion of the write burst. For the
generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
CLK
DQM
DQ
t_IS
t_IH
t_IS
t_IH
DI n
DI n+2
= Don't Care
Figure 24 Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
28
V1.4, 2004-04-30