HYB18L256160BF Datasheet, PDF (20/49 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

2.4.4 ACTIVE
CLK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
(High)
RA
BA
= Don't Care
BA = Bank Address
RA = Row Address
Figure 9 ACTIVE Command
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
Before any READ or WRITE commands can be issued
to a bank within the Mobile-RAM, a row in that bank
must be “opened” (activated). This is accomplished via
the ACTIVE command and addresses A0 - A12, BA0
and BA1 (see Figure 9), which decode and select both
the bank and the row to be activated. After opening a
row (issuing an ACTIVE command), a READ or WRITE
command may be issued to that row, subject to the t_RCD
specification. A subsequent ACTIVE command to a
different row in the same bank can only be issued after
the previous active row has been “closed”
(precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by t_RC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by t_RRD.
CLK
Command ACT
NOP
ACT
NOP
NOP
RD/WR
NOP
A0-A12 ROW
ROW
COL
BA0, BA1 BA x
BA y
BA y
t_RRD
t_RCD
= Don't Care
Figure 10 Bank Activate Timings
Table 9 Timing Parameters for ACTIVE Command
Parameter
Symbol
- 7.5
Units
min.
max.
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
t_RC
67
t_RCD
19
t_RRD
15
–
ns
–
ns
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
1)
1)
1)
Data Sheet
20
V1.4, 2004-04-30