TC1775 Datasheet, PDF (63/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
PLL Operation
The f_VCO clock of the PLL has a frequency which is a multiple of the externally applied
clock f_OSC. The factor for this is controlled through the value N applied to the divider in
the feedback path. N is defined through three PLL configuration inputs CLKSEL[2:0].
Table 7
Input Frequencies and N Factor for f_VCO
CLKSEL[2:0] N-Factor f_VCO = 150 MHz f_VCO = 160 MHz
f_VCO = 200 MHz
000_B
8
18.75
20
25
001_B
9
16.67
17.76
22.22
010_B
10
15
16
20
011_B
11
13.64
14.55
18.18
100_B
12
12.5
13.33
16.67
101_B
13
11.54
12.31
15.38
110_B
14
10.71
11.43
14.29
111_B
15
10
10.67
13.33
Shaded combinations should not be used because the maximum oscillator frequency of 16 MHz is exceeded.
The K-Divider is a software controlled divider. Table 8 lists the possible values for K and
the resulting division factor.
Table 8
Output Frequencies f_SYS Derived from Various Output Factors
K-Factor
Selected
Factor
KDIV
f_VCO =
150 MHz
f_SYS1)
f_VCO =
160 MHz
f_VCO =
200 MHz
Duty
Cycle
[%]
2
000_B
75
80
100
50
4
010_B
37.5
40
50
50
5²⁾
011_B
30
32
40
40
6
100_B
24.5
26.67
33.33
50
8
101_B
18.75
20
25
50
9²⁾
110_B
16.67
17.78
22.22
44
10
111_B
15
16
20
50
16
001_B
9.38
10
12.5
50
Shaded combinations cannot not be used because the maximum system clock frequency of 40 MHz is
exceeded.
1) _{Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must}
be selected as follows: f_SYS ≤ 30 MHz: ICR.CONECYC = 1, f_SYS > 30 MHz: ICR.CONECYC = 0.
2) _{These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).}
Data Sheet
59
V1.2, 2002-05