TC1775 Datasheet, PDF (62/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
Clock Generation Unit
The Clock Generation Unit (CGU) in the TC1775, shown in Figure 18, consists of an
oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses its lock on the external clock.
In general, the CGU is controlled through the System Control Unit (SCU) module of the
TC1775.
Clock Generation Unit
CGU
XTAL1
Oscillator ^fOSC
&
Circuit
XTAL2
Phase
Detect.
VCO
N
Divider
PLL
1
f_VCO ^MUX
0
K
Divider
1
MUX
0
System_
CLK
f_SYS
Lock
Detector
CLKSEL[2:0]
BYPASS
OSC_OK PLL Deep NDIV[2:0]
Locked Sleep
System Control Unit
SCU
VCO_ KDIV[2:0] PLL_
BYPASS
BYPASS
Register PLL_CLC
MCA04713
Figure 18 Clock Generation Unit Block Diagram
Besides the two XTAL pins for the oscillator, input pins CLKSEL[2:0] and BYPASS are
used for configuration of the clock generation unit. These inputs are checked by the SCU
which generates the appropriate control signals and latches the state of these signals
into register PLL_CLC.
Data Sheet
58
V1.2, 2002-05