TC1775 Datasheet, PDF (33/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
Serial Data Link Interface
Figure 8 shows a global view of the functional blocks of the Serial Data Link Interface
(SDLM).
C lo c k
Control
f_SDLM
Address
Decoder
Interrupt
Control
SDLM
M o du le
(K e rn e l)
RXD
Port
TXD ^Control
P12.10 /
RXJ1850
P12.11 /
TXJ1850
MCB04570
Figure 8 General Block Diagram of the SDLM Interface
The SDLM module communicates with the external world via two I/O lines located at
Port 12, the J1850 bus. The RXD line is the receive data input signal and TXD is the
transmit data output signal.
The Serial Data Link module (SDLM) provides serial communication to a J1850 based
serial bus. J1850 bus transceivers must be implemented externally in a system. The
SDLM module conforms to the SAE Class B J1850 Specification and is compatible to
Class 2 protocol.
General SDLM Features:
• Compliant to SAE Class B J1850 Specification
• Full support of GM Class 2 protocol
• Variable Pulse Width (VPW) format with 10.4 kbit/s
• High speed receive/transmit 4x mode with 41.6 kbit/s
• Digital noise filter
• Support of single byte headers or consolidated headers
• CRC generation and check
• Support of Block Mode for receive and transmit
Data Sheet
29
V1.2, 2002-05