TC1775 Datasheet, PDF (53/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
System Timer
The STM within the TC1775 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Driven by clock f_STM (identical with the system clock f_SYS)
• Counting begins at power-on reset
• Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency f_SYS. It is
enabled per default after reset, and immediately starts counting up. Other than via reset,
it is not possible to affect the contents of the timer during normal operation of the
application, it can only be read, but not written to. Depending on the implementation of
the clock control of the STM, the timer can optionally be disabled or suspended for
power-saving and debugging purposes via a clock control register.
The maximum clock period is 2⁵⁶ × 1/f_STM. At f_STM = 40 MHz, for example, the STM
counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
f_STM
PORST
STM Module
55
47
39
31
23
15
7
56-Bit System Timer
Enable/
Clock Disable
Control
Address
Decoder
00_H
CAP
00_H
TIM6
TIM5
TIM4
TIM3
TIM2
TIM1
TIM0
MCA04795
Figure 14 Block Diagram of the STM Module
Data Sheet
49
V1.2, 2002-05