TC1775 Datasheet, PDF (37/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
General Purpose Timer Array
Figure 10 shows a global block diagram of the General Purpose Timer Array (GPTA)
implementation.
C lo c k
C o n tro l
f_GPTA
Address
Decoder
GPTA Module Kernel
Clock G eneration Unit
Filter &
P re s c a le r
C e lls
Phase
D iscrim ina tor
Logic
Duty Cycle Digital Phase
M easurem ent Locked Loop
Interrupt
C o n tro l
SR00
SR01
SR52
SR53
A /D
C o n v e rte r
P T IN 0 0
P T IN 0 1
P T IN 1 0
P T IN 1 1
Signal G eneration Unit
G lobal Tim er
C e lls
Local Timer
C e lls
G lobal
Tim ers
Interrupt Control Unit
IN 0
IN 1
IN 6 2
IN 6 3
AS0
AS1
AS62
AS63
IO0 _P8.0
IO1 _P8.1
IO 1 4
IO 1 5
IO 1 6
IO 1 7
P8.14
P8.15
P9.0
P9.1
P o rt
C o n tro l
IO 3 0
IO 3 1
IO 3 2
IO 3 3
P9.14
P9.15
P 1 0 .0
P 1 0 .1
OUT0
OUT1
OUT62
OUT63
IO 4 6
IO 4 7
IO 4 8
IO 4 9
P 1 0 .1 4
P 1 0 .1 5
P 1 1 .0
P 1 1 .1
IO 6 2
IO63 ^P11.14
P 1 1 .1 5
MCB04490
Figure 10 GPTA Module Block Diagram
The GPTA module has 64 input lines and 64 output lines, which are connected with
Port 8, Port 9, Port 10, and Port 11.
The General Purpose Timer Array (GPTA) provides important digital signal filtering and
timer support whose combination enables autonomous and complex functionalities. This
architecture allows easy implementation and easy validation of any kind of timer
functions.
Data Sheet
33
V1.2, 2002-05