TC1775 Datasheet, PDF (21/101 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1775
Preliminary
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin
In Functions
Out
BYPASS W22 I
CFG0
CFG1
CFG2
CFG3
TRST³⁾
Y23 I
Y22 I
W21 I
W23 I
AA19 I
TCK³⁾
TDI⁴⁾
AB19 I
AC19 I
PLL Bypass Control Input
BYPASS is used for direct drive mode operation of the clock
circuitry. This pin is sampled during power-on reset
(PORST = low). Its level is latched into the PLL Clock
Control Register PLL_CLC. The combination BYPASS = 1
and CLKSEL[2:0] = 000_B during power-on reset is reserved.
Operation Configuration Inputs
The configuration inputs define the boot options of the
TC1775 after a hardware reset operation.
JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
JTAG Module Clock Input
JTAG Module Serial Data Input
TDO
AA18 O
TMS⁴⁾
AB20 I
OCDSE⁴⁾ Y19 I
BRKIN⁴⁾ AC20 I
JTAG Module Serial Data Output
JTAG Module State Machine Control Input
OCDS Enable Input
A low level on this pin during power-on reset (PORST = low)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
BRKOUT AC18 O
NMI⁴⁾
Y20 I
OCDS Break Output
A low level on this pin indicates that a programmable OCDS
event has occurred.
Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
Data Sheet
17
V1.2, 2002-05