TLE75008-EMD_15 Datasheet, PDF (47/64 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control

TLE75008-EMD
Serial Peripheral Interface (SPI)
CSN “low” to "high" Transition
• Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in “low” state whenever chip select CSN makes any transition, otherwise the
command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 10.5 for
further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin
goes to “low” state. New data appears at the SO pin following the rising edge of SCLK.
Please refer to Chapter 10.5 for further information.
10.2
Daisy Chain Capability
The SPI of TLE75008-EMD provides daisy chain capability. In this configuration several devices are activated by
the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 24), in order to build a chain. The end of the chain is connected to the output and input of the master device,
MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line
of each device in the chain.
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCSN
MCLK
SPI_DaisyChain_1.emf
Figure 24 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. The
bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished. In single
chip configuration, the CSN line must turn “high” to make the device acknowledge the transferred data. In daisy
Data Sheet
47
Rev. 1.1, 2015-09-25