TLE75008-EMD_15 Datasheet, PDF (41/64 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control

TLE75008-EMD
Protection Functions
switched ON after clearing the protection latch by setting the corresponding HWCR_OCL.OUTn bit to “1”. This bit is
set back to “0” internally after de-latching the channel.
8.3
Over Temperature and Over Load Protection in Limp Home mode
When TLE75008-EMD is in Limp Home mode, channels 2 and 3 can be switched ON using the input pins. In case
of Over Load, Short Circuit or Over Temperature the channels switch OFF. If the input pins remain “high”, the
channels restart with the following timings:
• 10 ms (first 8 retries)
• 20 ms (following 8 retries)
• 40 ms (following 8 retries)
• 80 ms (as long as the input pin remains “high” and the error is still present)
If at any time the input pin is set to “low” for longer than 2*t_SYNC, the restart timer is reset. At the next channel
activation while in Limp Home mode the timer starts from 10 ms again. See Figure 19 for details. Over Load
current thresholds behave as described in Chapter 8.1.
IN0
IN1
I_L2
I_L3
0
1
8
1
8
1
8
t
0
1
t _RETRY0(LH)
10 ms
t_{RETRY 1(LH)}
20 ms
t _RETRY2(LH)
40 ms
Figure 19 Restart timer in Limp Home mode
t_{RETRY 3(LH)}
80 ms
t_{RETRY 0(LH)}
t
10 ms
LHrestart.emf
8.4
Reverse Polarity Protection
In Reverse Polarity (also known as Reverse Battery) condition, power dissipation is caused by the intrinsic body
diode of each DMOS channel. Each ESD diode of the logic and supply pins contributes to total power dissipation.
The reverse current through the channels has to be limited by the connected loads. The current through digital
power supply V_DD and input pins has to be limited as well (please refer to the Absolute Maximum Ratings listed
on Chapter 4.1).
Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity.
8.5
Over Voltage Protection
In the case of supply voltages between V_S(SC) and V_S(LD) the output transistors are still operational and follow the
input pins or the OUT register.
In addition to the output clamp for inductive loads as described in Chapter 7.1.2, there is a clamp mechanism
available for over voltage protection for the logic and all channels, monitoring the voltage between VS and GND
pins (V_S(AZ)).
Data Sheet
41
Rev. 1.1, 2015-09-25