TLE75008-EMD_15 Datasheet, PDF (15/64 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control

TLE75008-EMD
General Product Characteristics
Table 2 Absolute Maximum Ratings (cont’d)¹⁾
T_J = -40 °C to +150 °C
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note /
Test Condition
Number
Input Pins
Voltage at input pins
V_IN
Current through input pins
I_IN
Current through input pins
I_IN
SPI Pins
-0.3
-0.75
-10.0
5.5
V
–
0.75 mA –
2.0
mA t ≤ 2 min.
P_4.1.28
P_4.1.30
P_4.1.31
Voltage at chip select pin
Current through chip select pin
Current through chip select pin
Voltage at serial clock pin
Current through serial clock pin
Current through serial clock pin
Voltage at serial input pin
Current through serial input pin
Current through serial input pin
Voltage at serial output pin SO
Current through serial output pin
SO
V_CSN
I_CSN
I_CSN
V_SCLK
I_SCLK
I_SCLK
V_SI
I_SI
I_SI
V_SO
I_SO
-0.3
-0.75
-10.0
-0.3
-0.75
-10.0
-0.3
-0.75
-10.0
-0.3
-0.75
5.5
V
0.75 mA
2.0
mA
5.5
V
0.75 mA
2.0
mA
5.5
V
0.75 mA
2.0
mA
V_DD+0.3 V
0.75 mA
–
–
t ≤ 2 min.
–
t ≤ 2 min.
–
t ≤ 2 min.
P_4.1.33
P_4.1.34
P_4.1.35
P_4.1.37
P_4.1.38
P_4.1.39
P_4.1.41
P_4.1.42
P_4.1.43
P_4.1.58
P_4.1.45
Current through serial output pin I_SO
-2.0
SO
10.0 mA t ≤ 2 min.
P_4.1.46
Temperatures
Junction Temperature
T_J
-40
– 150
°C –
P_4.1.48
Storage Temperature
T_stg
-55
– 150
°C –
P_4.1.49
ESD Susceptibility
ESD Susceptibility HBM
OUT pins vs. V_S or GND
ESD Susceptibility HBM
other pins
V_ESD
-4
–4
V_ESD
-2
–2
kV
5)
HBM
kV
5)
HBM
P_4.1.50
P_4.1.51
ESD Susceptibility CDM
Pin 1, 12, 13, 24 (corner pins)
V_ESD
-750 – 750
V
6)
CDM
P_4.1.52
ESD Susceptibility CDM
V_ESD
-500 – 500
V
6)
CDM
P_4.1.54
1) Not subject to production test, specified by design.
2) For a duration of t_on = 400 ms; t_on/t_off = 10%; limited to 100 pulses
3) Device is mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; the Product
(Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4) Pulse shape represents inductive switch off: I_L(t) = I_L(0) x (1 - t / t_pulse); 0 < t < t_pulse
5) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF)
6) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Data Sheet
15
Rev. 1.1, 2015-09-25