TC1724 Datasheet, PDF (42/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
Pinning
Table 3-1 Pin Definitions and Functions (PG-LQFP-144-17 package) (cont’d)
Pin Symbol
Ctrl. Type Function
24, V₅
60,
86
127
-
-
EVR Power Supply (5V)
25
V_PDG
80, V_SS
83
-
-
EVR Pass Device Gate
If this pin is connected to ground, the internal pass
devices are used and the external pass device
bypassed.
-
-
Digital Ground
81 XTAL1
I
Main Oscillator Input
82 XTAL2
O
Main Oscillator Output
88 TMS
DAP1
I
A2/ JTAG State Machine Control Input
I/O ^PD Device Access Port Line 1
90 TRST
I
A1/ JTAG Reset Input
PD
91 TCK
DAP0
I
A1/ JTAG Clock Input
I
PD _{Device Access Port Line 0}
94 TESTMODE I
I/PU Test Mode Select Input
96 ESR1
I/O A2/ External System Request Reset Input 1
PD
97 PORST
I
I/PU Power On Reset
98 ESR0
I/O A2 External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
1) Only applicable for SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR.
2) Analog input overlayed with digital input functionality. The related port logic is used to configure the input as
either analog input (default after reset) or digital input. The related port logic supports only the port input
features as the connected pads are input only pads.
3) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.
4) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.
5) For the emulation device (ED), this pin is bonded to VDD_SB (ED Stand By RAM supply). In the production
devide device, this pin is bonded to a VDD pad.
Data Sheet
3-25
V1.2, 2014-06