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TC1724 Datasheet, PDF (131/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1724
Electrical Parameters
⢠Corrected typo for Class D pads in PN-Junction Characteristics for positive/negative
overload tables
⢠Updated limits of IDD for max pattern, fCPU=133MHz, to max 310mA
⢠Updated limits of IDD for max pattern, fCPU=80MHz, to max 248mA
⢠Updated limits of PD for max pattern, fCPU=133MHz, to max 902mA
⢠Updated limits of IDD for max pattern, fCPU=80MHz, to max 810mA
⢠Corrected typo for COUT13
⢠Updated load jump current for COUT33 and COUT13 for fCPU=80MHz
⢠Changed min to typ value for CIN5
Changes from V0.6 to V0.7
⢠Name of package is updated
Changes from V0.7 to V0.8
⢠Absolute maximum rating section for is updated for VDDP, VIN, VAIN, VAREF0, VAINF
⢠A footnote is added to tERD
⢠A note is added, updated pad supply levels in Pin Reliability in Overload section
⢠Updated min limit for t17 of MLI
⢠Added a footnote to IDDP
⢠Included text to power sequencing sections for setting of P0.4 and P0.5.
⢠Added limits for EFDNLfor Gain= 4, 8
⢠Changed STT to tEVR, updated Power, Pad and Reset Timing figure
⢠Changed min limit of tL for PLL_ERAY timing
⢠Changed min limit of tL for PLL_Sysclk timing
⢠Removed IPU_VDPG for VDD5â¥2.97V, VDD5£3.63V
⢠Updated limit and test condition for COUT33, COUT13
⢠Updated limit for CIN5
⢠Updated limit and test condition for âVLOREG33
⢠Removed PSRR33, PSRR13
⢠Updated test condition for âVLOREG13
⢠Updated limit and test condition for âVLIREG13
⢠Updated min limit for MSC t45, strong sharp setting, CMOS mode
⢠Added âVOUT33, âVOUT13 parameters
⢠Updated first sentence for Chapter 5.3
⢠Added text for MLI and SSC parameters for validity of strong driver medium edge
only
⢠Updated description for t52 and t53
⢠Changed SSC parameters from CC to SR for t56, t57, t58, and t59
⢠Changed min to max limit for EVR Supply ramp-up parameter
⢠Updated min limit for IPU_VDPG
Changes from V0.8 to V1.0
⢠Added limits for EFGRAD for Gain= 4, 8
⢠Added limits for EFREFI
Data Sheet
5-86
V1.2, 2014-06
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