TC1724 Datasheet, PDF (105/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

5.3.7 Phase Locked Loop (PLL)
TC1724
Electrical Parameters
Table 31 PLL_SysClk Parameters
Parameter
Symbol
Min.
Accumulated Jitter D_P
CC -7
PLL base frequency f_PLLBASE CC 50
VCO input frequency f_REF
CC 8
VCO frequency
range
f_VCO
CC 400
PLL lock-in time
t_L CC
14
14
Values
Typ. Max.
−
7
200 320
−
16
−
720
−
200
−
400
Unit Note /
Test Condition
ns
MHz
MHz
MHz
μs N > 32
μs N ≤ 32
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the LMB-
Bus clock f_LMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter D_m in
[ns] dependent on the K2 - factor, the LMB clock frequency f_LMB in [MHz], and the
number m of consecutive f_LMB clock periods.
for
(K2 ≤ 100)
and
(m ≤ (f_LMB[MHz]) ⁄ 2)
Dm[ns]
=
⎛
⎝
-------------------7---4---0-------------------
K2 × f_LMB[MHz]
+
5_⎠⎞
×
⎛
⎝
-⁽--1----–-----0---^,---0---1----^×-----K-----2---⁾----^×-----⁽--m------–-----1----⁾
0, 5 × f_LMB[MHz] – 1
+
0,
01
×
K2_⎠⎞
(6)
else
Dm[ns] = -------------------7---4---0------------------- + 5
(7)
K2 × f_LMB[MHz]
Data Sheet
5-60
V1.2, 2014-06