TC1724 Datasheet, PDF (118/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
Electrical Parameters
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
t₅₀
SCLK¹⁾²⁾
t51
t51
MTSR¹⁾
MRST¹⁾
SLSOn²⁾
t52
t₅₃
Data
valid
t51
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 24 Master Mode Timing
Data Sheet
5-73
V1.2, 2014-06