TC1724 Datasheet, PDF (121/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
Electrical Parameters
5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * V_DDP to 80% * V_DDP, according to the FlexRay
Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have
to satisfy the following inequality: -1.6ns ≤ |t_FA2 - t_RA2| ≤ 1.3ns.
BSS
(Byte Start Sequence)
TXD
t_sample
TXD
t₆₁
BSS
(Byte Start Sequence)
RXD
t_sample
RXD
t₆₄
Last CRC Byte
t₆₀
Last CRC Byte
t₆₃
Figure 26 ERAY Timing
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
t₆₂
FES
(Frame End Sequence)
0.9 VDD
0.1 VDD
0.7 VDD
0.3 VDD
0.7 VDD
0.3 VDD
t₆₅
ERAY_TIMING
Data Sheet
5-76
V1.2, 2014-06