TC1724 Datasheet, PDF (16/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
System Overview of the TC1724
Figure 3 shows the block diagram of the SAK-TC1724N-192F80HL / SAK-TC1724N-
192F80HR.
ASC0
ASC1
PMI
16 KB SPRAM
8 KB ICACHE
(Configurable)
FPU
TriCore
CPU
TC1.3.1
80MHz
CPS
DMI
116 KB LDRAM
4 KB DCACHE
(Configurable)
Local Memory Bus (LMB)
PMU
1,5 MB PFlash
64 KB Dflash
16 KB BROM
8 KB OVRAM
LFI Bridge
LBCU
M
DMA
16 channels
M/S
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
SPRAM: Scratch-Pad RAM
LDRAM: Local Data RAM
OVRAM: Overlay RAM
BROM: Boot ROM
PFlash: Program Flash
DFlash: Data Flash
PRAM:
Parameter RAM in PCP
CMEM: Code RAM in PCP
1.3V, 3.3V
Int. Supply
Optional Ext. Supply
EVR
Embedded
Voltage
Regulator
5V, 3.3V
Single-source
Ext. Supply
OCDS L1 Debug
Interface
8 KB PRAM
PCP2
Core
System Peripheral Bus
(SPB)
Interrupt
System
STM
JTAG/DAP
MLI0
MemCheck
24 KB CMEM
SCU
CAPCOM
(CCU60, CCU61)
GPT12
(GPT 120)
GPT12
(GPT 121)
GPTA 0
SBCU
PLL
fCPU
Ext.
Request
Unit
MultiCAN
(3 Nodes,
64 MO)
MSC0
Ports
BMU
SSC0
SSC1
SSC2
SSC3
FCE
5V
Ext. ADC Supply
ADC0
(5V max,
16
16 channels )
ADC1
8
(5V max,
24 channels )
4
FADC
(3.3V max,
2 differential
channels )
BlockDiagram
TC1724N
V0.8
Figure 3 SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR Block Diagram
Data Sheet
2-4
V1.2, 2014-06